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Electronics
Semiconductor Division
RC5050
Programmable DC-DC Converter for Low Voltage Microprocessors
Features
* * * * * * * * * * Programmable output from 1.3V to 3.5V 85% efficiency typical 1% output accuracy Oscillator frequency adjustable from 80KHz to 1MHz On-chip Power Good and Enable functions Over-Voltage Protection Foldback current limiting Precision trimmed low TC voltage reference 20 pin SOIC package Meets Intel Pentium(R) II specifications using minimum number of external components
Description
The RC5050 is a DC-DC controller IC which provides an accurate, programmable output for all Pentium II CPU applications. The RC5050 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5050 uses a high level of integration to deliver load currents in excess of 15A from a 5V source with minimal external circuitry. Nonsynchronous operation allows a low cost solution for most CPU power supply applications. The internal oscillator can be programmed from 80KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5050 also offers integrated functions including Power Good, Output Enable, over-voltage protection and current limiting.
Applications
* Programmable power supply for Pentium II * Voltage Regulator Module (VRM) for Pentium II processors * Programmable step-down power supply
Block Diagram
+12V RC5050 OSC
- +
+5V
- +
- +
- +
DIGITAL CONTROL
VO
VREF
5-BIT DAC
1.24V REFERENCE
POWER GOOD
PWRGD
65-5050-01
VID0 VID2 VID4 VID1 VID3
ENABLE
Pentium is a registered trademark of Intel Corporation.
Rev. 1.2.1
RC5050
PRODUCT SPECIFICATION
Pin Assignments
CEXT ENABLE PWRGD IFB VFB VCCA VCCD VID4 NC GNDP
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
65-5050-02
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP HIDRV NC
Pin Definitions
Pin Number 1 Pin Name CEXT Pin Function Description Oscillator Capacitor Connection. Connecting an external capacitor to this pin sets the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details. Output Enable. Open collector/TTL input. Logic LOW will disable output. A 10K internal pull-up resistor assures correct operation if pin is left unconnected.
2 3 4
ENABLE
PWRGD Power Good Flag. Open collector output will be at logic HIGH under normal operation. Logic LOW indicates output voltage is not within 12% of nominal. IFB High Side Current Feedback. Pins 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Layout of these traces is critical to system performance. See Application Information for details. Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. Layout of this trace is critical to system performance. See Application Information for details. Analog Vcc. Connect to system 5V supply and decouple to ground with 0.1F ceramic capacitor. Digital Vcc. Connect to system 5V supply and decouple to ground with 4.7F tantalum capacitor. VID4 Input. A logic 1 on this open collector/TTL input will enable the VID3-VID0 inputs to set the output from 2.1V to 3.5V, and a logic 0 on this pin will set the output from 1.3V to 2.05V, as shown in Table 1. Pullup resistors are internal to the controller. No Internal Connection. Connection of these pins to system ground will improve the thermal dissipation characteristics of the package. Power Ground. Return pin for high currents flowing in pins 12 and 13 (HIDRV and VCCQP). Connect to low impedance ground. FET Driver Output. Connect this pin to the gates of N-channel MOSFETs M1 and M2 in Figure 1. The trace from this pin to the MOSFET gates should be < 0.5". Power Vcc. This is the power supply for the FET driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (M1). See Application Information for details. Digital Ground. Return path for digital logic. This pin should be connected to system ground to minimize ground loops. Analog Ground. Return path for low power analog circuitry. Connect to system ground to minimize ground loops. Reference Voltage Test Point. This pin provides access to the DAC output and should be decoupled to ground using a 0.1F capacitor. No load should be connected. Voltage Identification (VID) Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Pullup resistors are internal to the controller.
5
VFB
6 7 8
VCCA VCCD VID4
9, 11 10 12 13 14 15 16 17-20
NC GNDP HIDRV VCCQP GNDD GNDA VREF VID3- VID0
2
PRODUCT SPECIFICATION
RC5050
Absolute Maximum Ratings
Supply Voltages, VCCA, VCCD, VCCQP Voltage Identification Code Inputs, VID4-VID0 Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds 13V 13V 150C -65 to 150C 300C
Operating Conditions
Parameter Supply Voltages, VCCA and VCCD Output Driver Supply, VCCQP Input Logic HIGH Input Logic LOW PWRGD Threshold Ambient Operating Temperature Logic HIGH Logic LOW 93 88 0 Conditions Min. 4.5 8.5 2.0 0.8 107 112 70 Typ. 5 Max. 7 12 Units V V V V %VO %VO C
Electrical Characteristics
(VCCA, VCCD = 5V, VOUT = 2.8V, Fosc = 300 KHz, and TA = +25C using Figure 1, unless otherwise specified) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint Output Temperature Drift Load Regulation Line Regulation Output Ripple Output Voltage Regulation Steady State1 Transient2 Short Circuit Detect Threshold Efficiency Output Driver Rise and Fall Time Turn-on Response Time Oscillator Range Oscillator Frequency Max Duty Cycle CEXT = 100 pF PWM mode ILOAD = 13A, VOUT = 2.8V See Figure 2 ILOAD = 0 to 13A 80 270 90 300 300 95 ILOAD = 0.8A TA = 0 to 60C ILOAD = 0.8A to 13A VIN = 4.75 to 5.25V 20MHz BW, ILOAD = 13A VOUT = 2.8V, ILOAD = 0.8 - 15A ILOAD = 0.8 to 14.2A, 30A/s * * * * 2.74 2.67 100 80 * * * Conditions See Table 1 * Min. 1.3 13 20 +10 -25 2 11 2.80 2.80 120 85 50 10 1000 330 2.90 2.93 140 Typ. Max. 3.5 Units V A mV mV mV mV mV V V mV % ns ms KHz KHz %
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, output ripple/noise and temperature drift. 2. These specifications assume a minimum of 20, 1F ceramic capacitors are placed directly next to the CPU in order to provide adequate high-speed decoupling. For motherboard applications, the PCB layout must exhibit no more than 0.5m parasitic resistance and 1nH parasitic inductance between the converter output and the CPU.
3
RC5050
PRODUCT SPECIFICATION
Table 1. Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VOUT to CPU 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V No CPU 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND 1 = processor pin is open.
4
PRODUCT SPECIFICATION
RC5050
Typical Operating Characteristics
(VCCA, VCCD = 5V, fosc = 280 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current
92.0 90.0 VOUT = 3.3V 2.83 2.82 2.81 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73
Load Regulation, VOUT = 2.8 V
Efficiency (%)
88.0 84.0 82.0 80.0 78.0 76.0 74.0 1 3 5 7 9 11 13 14.5
VOUT = 2.5V
VOUT (V)
86.0
VOUT = 2.8V
1
3
5
7
9
11
13
14.5
Output Current (A) Output Voltage vs. Output Current, RSENSE = 6m
3.5 1250 3.0 2.5 1050 850 650 450 250 50 0 5 10 15 20 25 18 39
Output Current (A)
Oscillator Frequency vs. CEXT
2.0 1.5 1.0 0.5 0
Frequency (KHz)
VOUT (V)
75
150
300
561
Output Current (A)
CEXT (pf)
Output Programming, VID4 = 0
3.5 3.0 3.5 3.0
Output Programming, VID4 = 1
VOUT (V)
2.5 2.0 1.5 1.0 1.30
VOUT (V)
1.40 1.50 1.60 1.70 1.80 1.90 2.0
2.5 2.0 1.5 1.0
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
DAC Set Point
DAC Set Point
65-5050-03
5
RC5050
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Output Ripple, 2.8V @ 13A Transient Response, 0.5A to 13A
VOUT (20mV/div)
VOUT (50mV/div)
Time (2s/division)
Time (50s/division)
Switching Waveforms, 0.5A Load
Switching Waveforms, 13A Load
500mV/div
CEXT pin
500mV/div
CEXT pin
20mV/div
HDRV pin
20mV/div
HIDRV pin
Time (2s/division)
Time (2s/division)
Output Startup, System Power-up
Output Startup from Re-enable
VOUT (1V/div)
ENABLE (1V/div)
VIN (1V/div )
VOUT (1V/div)
Time (10ms/division)
Time (10ms/division)
65-5050-04
6
PRODUCT SPECIFICATION
RC5050
Test Circuit
+12V L2 +5V 2.5H C4 0.1F CIN C5 0.1F R5 47 D1 1N4735A C8 0.1F C9 0.1F
M1 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 IRL3103
M2 IRL3103 L1 RSENSE* VO
C6 1F
C12 1F
1.3H DS1 MBR2015CTL
RC5050
VREF C7 GND 0.1F
COUT*
CEXT 100pF
VID4 VID3 VID2 VID1 VID0 C10 0.1F ENABLE C11 0.1F R6 10K
VCC
PWRGD
*Refer to Table 2 for value of RSENSE, COUT, and CIN.
65-5050-12
Figure 1. 15A Application Circuit for Pentium II Processor
+12V 0.1F 47 1F VCCQP +5V 0.1F VCCA HIDRV RC5050 VCCD 4.7F GNDA GNDD GNDP
65-5050-11
tR HIDRV RISE/FALL 7000pF 10% 90% 50% 90% 50%
tF
10%
Figure 2. Output Driver Test Circuit
Table 2. Recommended Bulk Capacitors for CPU-based Applications
Application Motorola PowerPC 603/604 Motherboard Intel Pentium II Klamath Motherboard Intel Pentium II Motherboard (All versions including next generation) Output Current 7A CIN 2 x 1500F, 6V Sanyo 6MV1500CX 3 x 1200F, 10V Sayno 10MV1200EG 3 x 1200F, 10V Sayno 10MV1200EG COUT 2 x 1500F, 6V Sanyo 6MV1500SX 5 x 1500F, 6.3V Sanyo 6MV1500GX 7 x 1500F, 6.3V Sanyo 6MV1500GX COUT Maximum ESR 22m RSENSE 10.5m
14.2
9.0m
5.5m
15A
6.0m
5.0m
7
RC5050
PRODUCT SPECIFICATION
Table 3. RC5050 Application Bill of Materials for Intel Pentium II Processors
Reference C4, C5, C7-C11 Cext C12, C6 CIN COUT DS1 D1 L1 L2 M1, M2 Manufacturer Part # Panasonic ECU-V1H104ZFX Panasonic ECU-V1H121JCG Panasonic ECSH1CY105R Sanyo 10MV1200EG Sanyo 6MV1500GX Motorola MBR2015CT 1N4735A Skynet 320-8107 Skynet 320-6110 International Rectifier IRL3103 Copel AWG#18 Panasonic ERJ-6GEY050Y Panasonic ERJ-6ENF10.0KV Description 0.1F 50V capacitor 100pF capacitor 1F 16V capacitor 1200F 10V electrolytic capacitor 10mm x 20mm 1500F 6.3V electrolytic capacitor 10mm x 20mm Schottky Diode 6.2V Zener Diode, Motorola 1.3H, 14A inductor DCR ~ 2.5m 2.5H, 11A inductor DCR ~ 6m N-Channel Logic Level Enhancement Mode MOSFET 5.5m CuNi Alloy Wire Resistor 47 5% resistor 10K 5% resistor See Note 2 See Note 3 RDS(ON) < 19m VGS < 4.5V, ID = 15A See Note 4 ESR < 62m See Table 2 ESR < 44m See Note 1 and Table 2 Vf < 0.52 at If = 10A Requirements/Comments
RSENSE R5 R6
Notes: 1. In order to meet the voltage transient requirements for the Intel Pentium II Motherboard application, the equivalent ESR of the output capacitors must not exceed 7.5m. In order to satisfy the specified Output Voltage Regulation requirements for VOUT = 1.8V at 15A for next generation processors, the output capacitors must exhibit no more than 6.0m equivalent ESR for a motherboard application. The use of the capacitors recommended in Table 1 will address this and other voltage specifications without significant added cost, although it is left up to the user to specify the components used. Please refer to Application Bulletin 5 for additional considerations required to meet the Intel Pentium II voltage transient specifications. 2. To optimize a converter for 15A at 1.8V output, fSW = 300 kHz, change the value of L1 to 1.24H. 3. Inductor L2 is recommended to isolate the 5V input supply from current surges caused by MOSFET switching. L2 is not required for normal operation and may be omitted if desired. 4. For 15A designs using IR3103 MOSFETs, heat sinks with thermal resistance SA < 50C/W should be used.
Application Information
Simple Step-Down Converter
S1 L1 + VIN D1 C1 RL Vout -
65-5050-06
Figure 3 illustrates a step-down DC-DC converter with no feedback control. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5050. Referring to Figure 3, the basic operation begins by closing the switch S1. When S1 is closed, the input voltage VIN is impressed across inductor L1. The current flowing in this inductor is given by the following equation: ( V IN - V OUT )T ON I L = ---------------------------------------------L1 where TON is the duty cycle (the time when S1 is closed).
Figure 3. Simple Buck DC-DC Converter
8
PRODUCT SPECIFICATION
RC5050
When S1 opens, the diode D1 will conduct the inductor current and the output current will be delivered to the load according to the equation: V OUT ( T S - T ON ) I L = ------------------------------------------L1 where TS is the overall switching period and (TS - TON) is the time during which S1 is open. By solving these two equations, we can arrive at the basic relationship for the output voltage of a step-down converter: T ON VOUT = V IN ---------- TS In order to obtain a more accurate approximation for VOUT, we must also include the forward voltage VD across diode D1 and the switching loss, Vsw. After taking into account these factors, the new relationship becomes: T ON V OUT = ( V IN + V D - V SW ) ---------- - V D TS where VSW = MOSFET switching loss = IL * RDS,ON
The additional comparators in the analog control section set the point at which the max current comparator disables the output drive signals to the external power MOSFETs. The digital control block is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV output pin that controls the external power MOSFET(s). The digital section was designed utilizing high speed Schottky transistor logic, thus allowing the RC5050 to operate at clock speeds as high as 1MHz.
High Current Output Drivers
The RC5050 contains a high current output driver which utilizes high speed bipolar transistors arranged in a push-pull configuration. This driver is capable of delivering 1A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for additional switching noise immunity. The output driver power supply, VCCQP, is derived from an external 12V supply through a 47 series resistor. The resulting voltage is sufficient to provide the gate-source voltage to the external MOSFET required in order to achieve a low RDS,ON.
Internal Voltage Reference
The reference included in the RC5050 is a precision bandgap voltage reference. The internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference output is the resulting output from an integrated 5-bit DAC. The DAC is provided in order to allow the DC-DC converter output to be directly programmable via a 5-bit digital input. When the VID4 pin is in the HIGH state, pins VID3-VID0 will scale the output voltage from 2V to 3.5V in 100mV increments. When the VID4 pin is pulled LOW, the output can be programmed from 1.3V to 2.05V in 50mV steps. For guaranteed stable operation under all operating conditions, a 0.1F decoupling capacitor should be connected to the VREF pin. No load should be imposed upon this pin.
The RC5050 Controller
The RC5050 is a programmable DC-DC controller IC. When designed around the appropriate external components, The RC5050 can be configured to deliver more than 14.5A of output current. The RC5050 utilizes both current-mode and voltage-mode control to create an integrated step-down voltage regulator. During heavy loading conditions, the RC5050 functions as a PWM step down regulator. Under light loads, the controller goes into Pulse Frequency Modulation (PFM) or pulse-skipping mode. The controller will sense the load level and switch between the two modes automatically, thus optimizing its efficiency under all conditions.
Main Control Loop
For this discussion, refer to the Block Diagram on page 1 of the data sheet. The control loop of the regulator contains two main sections; the analog control block and the digital control block. The analog block consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The voltage control path amplifies the VFB signal and presents the output to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block.
Power Good (PWRGD)
The RC5050 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a constant voltage monitor on the VFB pin. The internal circuitry compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage exceed 10% of its nominal setpoint. The Power Good flag provides no other control function to the RC5050.
Output Enable (ENABLE)
Intel specifications state that the DC-DC converter should accept an open collector signal for controlling the output voltage; a logic LOW on the ENABLE pin disables the output voltage. When disabled, the PWRGD output is in the low state.
9
RC5050
PRODUCT SPECIFICATION
Upgrade Present
Intel specifications state that the DC-DC converter should accept an open collector signal (UP#), used to indicate the presence of an upgrade processor. The typical state is high (standard processor). When in the low or ground state (OverDrive processor present), the output voltage must be disabled unless the converter can supply the OverDrive processor's power requirements. Because the RC5050 can supply the OverDrive processor requirements, the UP# signal is not required.
Design Considerations and Component Selection
MOSFET Selection
This application requires the use of N-channel, Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS,ON< 37 m (lower is better). * Low gate drive voltage, VGS 4.5V. * Power package with low Thermal Resistance. * Drain current rating of 20A minimum. * Drain-Source voltage > 15V The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation of the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. Table 4 presents a list of suitable MOSFETs for this application.
Over-Voltage Protection
The RC5050 provides a constant monitor of the output voltage for protection against over voltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an over-voltage condition will be assumed and the RC5050 will disable the output drive signal to the external MOSFET(s).
Short Circuit Protection
A current sense methodology is implemented to disable the output drive signal to the MOSFET(s) when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When the voltage developed across the sense resistor exceeds the 120 mV comparator threshold voltage, the RC5050 will reduce the output duty cycle to protect the power devices.
Two MOSFETs in Parallel
At higher load currents, it is recommend that two MOSFETs be used in parallel instead of a single MOSFET. Significant advantages are realized using two MOSFETs in parallel: * Significant reduction of power dissipation. Maximum current of 15A with one MOSFET: PMOSFET = (I2 RDS,ON)(Duty Cycle) = (15)2(0.050*)(2.8+0.4)/(5+0.4-0.35) = 7.1 W With two MOSFETs in parallel:
The DC-DC converter will return to normal operation after the fault has been removed, for either an over voltage or a short circuit condition.
Oscillator
The RC5050 oscillator section is implemented using a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to preset the oscillator frequency between 80KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency as well as in choosing external components. In general, a lower operating frequency will increase the peak ripple current flowing in the output inductor and thus require the use of a larger inductor value. Operation at lower frequencies also increases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to the slower loop response of the controller. Additionally, the efficiency losses due to switching of the MOSFETs will increase as the operating frequency is increased. Therefore, efficiency will be optimized at lower operating frequencies. Due to the trend of increasing load current at lower supply voltages, an operating frequency of 300 KHz has been chosen to optimize efficiency while maintaining excellent output regulation and transient performance. 10
PMOSFET = (I2 RDS,ON)(Duty Cycle) = (15/2)2(0.037*)(2.8+0.4)/(5+0.4-0.35) = 1.3W/FET
* Note: RDS,ON increases with temperature. Assume RDS,ON = 25m at 25C. RDS,ON can easily increase to 50m at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the temperature effects should not cause the RDS,ON to rise above the listed maximum value of 37m.
* No added heat sink required. With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, no external heat sink is required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2C/W and the motherboard serves as an excellent heat sink. * Higher current capability. With thermal management under control, this on-board DC-DC circuit is able to deliver load currents up to 15A with no performance or reliability concerns.
PRODUCT SPECIFICATION
RC5050
Table 4. MOSFET Selection Table
RDS, ON (m) Manufacturer & Model # Fuji 2SK1388 Siliconix SI4410DY National Semiconductor NDP706AL NDP706AEL National Semiconductor NDP603AL National Semiconductor NDP606AL Motorola MTB75N03HDL Int. Rectifier IRLZ44 Int. Rectifier IRL3103S VGS=4.5V, ID=28A VGS=5V, ID=31A VGS=5V, ID=37.5A VGS=5V, ID=24A VGS=4.5V, ID=10A Conditions1 VGS=4V, ID=17.5A VGS=4.5V, ID=5A VGS=5V, ID=40A TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C Typ. 25 37 16.5 28 13 20 31 42 22 33 6 9.3 -- -- -- Max. 37 -- 20 34 15 24 40 54 25 40 9 14 28 46 19 31 TO-220 TO-263 (D PAK)
2
Package TO-220 SO-8 (SMD) TO-220
Thermal Resistance JA=75 JA=50 JA=62.5 JC=1.5 JA=62.5 JC=2.5 JA=62.5 JC=1.5 JA=62.5 JC=1.0 JA=62.5 JC=1.0 JA=62.5 JC=1.0
TO-220 TO-220
TO-220
Note: 1. RDS,ON values at Tj = 125C for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only.
MOSFET Gate Bias
Figure 4 illustrates how an external 12V supply is used to bias the output driver supply, VCCQP. A 47 resistor is used to limit the transient current into the VCCQP pin and a 1F capacitor filter is used to filter the VCCQP supply. This method provides a sufficient gate-to-source bias voltage (VGS ) to the MOSFET, and therefore reduces the RDS,ON and the resulting power loss within the MOSFET. Figure 5 illustrates how the RDS,ON decreases dramatically as VGS increases. A 6.2V Zener (D1) is used to clamp the voltage at VCCQP to a maximum of 12V, thus ensuring that the absolute maximum voltage limit of the IC will not be exceeded.
+12V
+5V 47 D1 6.2V M1 HIDRV 1F PWM/PFM Control DS1 L1 RS VO CB
VCCQP
65-5050-07
Figure 4. MOSFET Gate Bias Configuration
11
RC5050
PRODUCT SPECIFICATION
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 5 6
Fuji Fuji 706A 706AEL
RDS,ON ()
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed range in order to maximize either ripple or transient performance. The first order equation (close approximation) for minimum inductance is: ( V OUT - V IN ) VOUT ESR L min = ----------------------------------- x -------------- x ---------V IN f Vr where: * * * * VIN = Input Power Supply VOUT = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel * Vr = Peak to peak output ripple voltage budget.
7
8
9
10 11
Gate-Source Voltage, VGS (V)
Figure 5. RDS,ON vs. VGS for Selected MOSFETs
Converter Efficiency
Losses due to parasitic resistance in the switches, inductor coil and sense resistor dominate at high load current levels. The major loss mechanisms under heavy loads, in usual order of importance, are: * * * * * * * * MOSFET I2R losses Inductor coil losses Sense resistor losses Gate-charge losses Diode-conduction losses Transition losses Input capacitor losses Losses due to the operating supply current of the IC.
The first order equation for maximum allowed inductance is: ( V IN - V OUT )D m V tb L min = 2Co x ---------------------------------------------------Ip2 where: * Co = The total output capacitance * Ip = Peak to peak load transient current * Vtb = The output voltage tolerance budget allocated to load transient * Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained between Lmin and Lmax. Adding margin by increasing Lmax almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase Lmax. Adding margin by decreasing Lmin can either be done by purchasing capacitors with lower ESR or by increasing the DC/DC converter switching frequency. The RC5050 is capable of running at high switching frequencies and provides significant cost savings for the newer CPU systems that typically run at high supply current.
The following sections provide details of these dominant loss components.
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-DC converter application.. The critical parameters are inductance (L), maximum DC current (Io) and the DC coil resistance (Rl). The inductor core material is a crucial factor in determining the amount of current the inductor will be able to withstand. As with all engineering designs, tradeoffs exist between various types of core materials. In general, Ferrites are popular due to their low cost, low EMI properties and high frequency (>500KHz) characteristics. Molypermalloy powder (MPP) materials exhibit good saturation characteristics, low EMI and low hysteresis losses; however, they tend to be expensive and more effectively utilized at operating frequencies below 400KHz. Another critical parameter is the DC winding resistance of the inductor. This value should typically be reduced as much as possible, as the power loss in the DC resistance will degrade the efficiency of the converter by the relationship: PLOSS = IO2 x Rl.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to provide continuous protection against short circuit conditions that may damage the CPU. To address this requirement, Raytheon has implemented a current sense methodology to limit the power delivered to the load in the event of an overcurrent condition. The voltage drop created by the output current flowing across a sense resistor is presented to one terminal of an internal comparator with hysterisis. The other comparator terminal has a threshold voltage, nominally 120mV. Table 6 states the limits for the comparator threshold of the Switching Regulator.
12
PRODUCT SPECIFICATION
RC5050
Table 6. RC5050 Short Circuit Comparator Threshold Voltage
Short Circuit Comparator Vthreshold (mV) Typical Minimum Maximum 120 100 140
The calculation of this ripple current is as follows:
( V IN - V SW - V OUT ) ( V OUT + V D ) ( I pk - I min ) --------------------------- = ---------------------------------------------------- x ---------------------------------------------- x T L ( V IN - V SW + V D ) 2
where: * Vin = input voltage to converter * VSW = voltage across the MOSFET = ILOAD x RDS,ON * VD = Forward Voltage of the Schottky diode * T = the switching period of the converter = 1/fS, where fS = switching frequency. For an input voltage of 5V, an output voltage of 2.8V, an inductor value of 1.3H and a switching frequency of 285KHz (using CEXT = 100pF), the inductor current can be calculated as follows: ( I pk - I min ) ( 5.0 - 14.5 x 0.037 - 2.8 ) --------------------------- = ------------------------------------------------------------- x -6 2 1.3 x 10 ( 2.8 + 0.5 ) 1 ------------------------------------------------------------- x ----------------------- 3A ( 5.0 - 14.5 x 0.037 + 0.5 ) 285 x 103 Therefore, for a continuous load current of 14.5A, the peak current through the inductor, Ipk, is found to be:
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------- = 14.5 + 3 = 17.5A 2
When designing the external current sense circuitry, the designer must pay careful attention to the output limitations during normal operation and during a fault condition. If the short circuit protection threshold current is set too low, the DC-DC converter may not be able to continuously deliver the maximum CPU load current. If the threshold level is too high, the output driver may not be disabled at a safe limit and the resulting power dissipation within the MOSFET(s) may rise to destructive levels. The design equation used to set the short circuit threshold limit is as follows: V th -, R SENSE = ------- where: I SC = Output short circuit current I SC ( I pk - I min ) I SC I inductor = I Load, max + --------------------------2 where Ipk and Imin are peak ripple current and Iload, max = maximum output load current The designer must also take into account the current (Ipk -Imin), or the ripple current flowing through the inductor under normal operation. Figure 6 illustrates the inductor current waveform for the RC5050 DC-DC converter at maximum load.
Ipk
For continuous operation at 14.5A, the short circuit detection threshold must be at least 17.5A. The next step is to determine the value of the sense resistor. Including tolerance, the sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- x ( 1 - TF ) = ---------------------------------- x ( 1 - TF ) I SC 3.0 + I Load,max
I
(Ipk-Imin)/2 Imin TON T=1/f s TOFF I LOAD, MAX t
where TF = Tolerance Factor for the sense resistor. There are several different types of sense resistors. Table 7 describes tolerance, size, power capability, temperature coefficient and cost of various sense resistors.
Figure 6. Typical DC-DC Converter Inductor Current Waveform
13
RC5050
PRODUCT SPECIFICATION
Table 7. Comparison of Sense Resistors
Discrete Iron Alloy resistor (IRC) 5% (1% available) 0.45" x 0.065" x 0.200" 1 watt (3W and 5W available) +30 ppm $0.31 Discrete Metal Strip surface mount resistor (Dale) 1% 0.25" x 0.125" x 0.025" 1 watt 75 ppm $0.47 Discrete MnCu Alloy wire resistor 10% 0.200" x 0.04" x 0.160" 1 watt 30 ppm $0.09 Discrete CuNi Alloy wire resistor (Copel) 10% 0.200" x 0.04" x 0.100" 1 watt 20 ppm $0.09
Description Tolerance Factor (TF) Size (L x W x H) Power capability Temperature Coefficient Cost @10,000 piece
Motherboard Trace Resistor 29% 2" x 0.2" x 0.001" (1 oz Cu trace) >50A/in +4,000 ppm Low included in motherboard
Based on the Tolerance in the above table: * For an embedded PC trace resistor and Iload,max = 14.5A: V th,min R SENSE = ---------------------------------------- x ( 1 - TF ) = 3.0A + I Load, max 100mV --------------------------------- x ( 1 - 29% ) = 4.1m 3.0A + 14.5A * For a discrete resistor and Iload, max = 14.5A: V th,min RSENSE = ---------------------------------------- x ( 1 - TF ) = 3.0A + I Load, max 100mV --------------------------------- x ( 1 - 5% ) = 5.4m 3.0A + 14.5A For user convenience, Table 8 lists the recommended values for sense resistor values at various load currents using an embedded PC trace resistor or discrete resistor.
RC5050 Short Circuit Current Characteristics
The RC5050 has a short circuit current characteristic that includes a foldback function with hysteresis that prevents the DC-DC converter from oscillating in the event of a short circuit. A typical V-I characteristic of the DC-DC converter output using a sense resistor value of 6m is presented in the Typical Operating Characteristics section, page 5. The converter performs with a typical voltage regulation characteristic until the voltage across the resistor exceeds the internal short circuit comparator threshold of 120mV. At this point, the internal comparator trips and sends a signal to the controller to turn off the gate drive to the power MOSFET. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. The output voltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the DC-DC converter.
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, DS1. DS1 is used as a flyback diode to provide a constant current path for the inductor when M1 is turned off. A vital selection criteria for DS1 is that it exhibits a very low forward voltage drop, as this parameter will directly impact the regulator efficiency as the output voltage is reduced. Table 9 presents several suitable Schottky diodes for this application. Note that the diode MBR2015CTL has a very low forward voltage drop. This diode is most ideal for applications where output voltages below 2.8V are required.
Table 8. Rsense for Various Load Currents
ILoad,max (A) 10.0 11.2 12.4 13.9 14.0 14.5 RSENSE PC Trace Resistor (m) 5.5 5.0 4.6 4.2 4.2 4.1 RSENSE Discrete Resistor (m) 7.3 6.7 6.2 5.6 5.6 5.4
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PRODUCT SPECIFICATION
RC5050
Table 9. Schottky Diode Selection Table
Manufacturer Model # Philips PBYR1035 Motorola MBR2035CT Motorola MBR1545CT Conditions IF = 20A; Tj=25C IF = 20A; Tj=125C IF = 20A; Tj=25C IF = 20A; Tj=125C IF = 15A; Tj=25C IF = 15A; Tj=125C Forward Voltage VF < 0.84V < 0.72V < 0.84V < 0.72V < 0.84V < 0.72V < 0.58V < 0.48V
where: * V is the maximum voltage deviation due to load transients * T is the reaction time of the power source (Loop response time of the RC5050), approximately 2s * IO is the output load current. For IO = 12.2A (0.8 to 13A) and V = 100mV, the bulk capacitance required can be approximated as follows:
I O x T 12.2 x 2s C ( F ) = ------------------------------------- = --------------------------------------------------------------- = 3200F V - I O x ESR 100mV - 12.2A x 7.5m
Motorola IF = 20A; Tj=25C MBR2015CTL IF = 20A; Tj=150C
Input Filter
It is recommended that the design include an input inductor between the system +5V supply and the DC-DC converter input described below. This inductor will serve to isolate the +5V supply from noise occurring in the switching portion of the DC-DC converter and also to limit the inrush current into the input capacitors during power up. An inductor value of around 2.5H is recommended, as illustrated below.
5V 2.5H Vin
Output Filter Capacitors
Optimal ripple performance and transient response are functions of the filter capacitors used. Since the 5V supply of a PC motherboard may be located several inches away from the DC-DC converter, input capacitance can play an important role in the load transient response of the RC5050. The higher the input capacitance, the more charge storage is available for improving the current transfer through the FET(s). Low "ESR" capacitors are best suited for this type of application and incorrect selection can influence the converter's overall performance. The input capacitor should be placed as close to the drain of the FET as possible to reduce the effect of ringing caused by long trace lengths. The ESR rating of a capacitor is a difficult number to quantify. ESR or Equivalent Series Resistance, is defined as the resonant impedance of the capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for this device to have a resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained using the following equation: DF ESR = -----------2fC where: * DF is the dissipation factor of the capacitor * f is the operating frequency * C is the capacitance in farads. With this in mind, correct calculation of the output capacitance is crucial to the performance of the DC-DC converter. The output capacitor determines the overall loop stability, output voltage ripple and load transient response. The calculation is as follows: I O x T C ( F ) = ------------------------------------V - I O x ESR
0.1F
1000F, 10V Electrolytic
65-5050-09
PCB Layout Guidelines and Considerations
PCB Layout Guidelines
1. Placement of the MOSFETs relative to the RC5050 is critical. The MOSFETs (M1 & M2), should be placed such that the trace length of the HIDRV pin from the RC5050 to the FET gates is minimized. A long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the large gate capacitance of the FET(s). This noise will radiate all over the board and will be very difficult to suppress, especially when the oscillator frequency is increased. Figure 7 depicts an example of proper placement of the MOSFETs in relation to the RC5050 as well as an example of incorrect placement of the MOSFETs. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5050. That is to say, traces that connect to pins 12 and 13 (HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 5, and pin 16.
15
RC5050
PRODUCT SPECIFICATION
Correct layout
11 12 13 14 15 16 17 18 19 20 RC5050 10 9 8 7 6 5 4 3 2 1
Poor layout
11 12 13 14 15 16 17 18 19 20 RC5050 10 9 8 7 6 5 4 3 2 1
= "Quiet" Pins
65-5050-10
Figure 7. Examples of Good and Bad MOSFET Layout
2.
Place decoupling capacitors (0.1F) as close to the RC5050 pins as possible. Extra lead length on these capacitors will negate their ability to suppress noise. Each VCC and GND pin should have its own via down to the appropriate plane underneath. This will help to add isolation between pins. The CEXT timing capacitor should be surrounded with a ground trace if possible. The placement of a ground or power plane underneath the capacitor will also provide further noise isolation. This will help to shield the oscillator from the noise on the PCB. This capacitor should be placed as close to pin 1 as possible. Group the MOSFETs, inductor and Schottky as close together as possible for the same reasons as #1 above. Also place the input bulk capacitors as close to the drains of MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each MOSFET will help to suppress some of the high frequency switching noise on the input of the DC-DC converter. The traces that run from the RC5050 IFB (pin 4) and VFB (pin 5) pins should be run together next to each other and be Kelvin connected to the sense resistor. Running these lines together will help in rejecting some of the common noise that is presented to the RC5050 feedback input. Try as much as possible to run the noisy switching signals (HIDRV & VCCQP) on one layer and use the inner layers for power and ground only. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals VFB and IFB.
PC Board Layout Checklist
* Bypass Capacitor near Vref pin. This pin should be adequately bypassed with a 0.1F capacitor. * Bypass Capacitors for VCC (5V). A 0.1F should be placed right next to the VCC pin of the controller. * Bypass Capacitors for Power MOSFET. A 0.1F cap should be placed at the drain connection of each power MOSFET. * 5V Connection to the controller IC. Each VCC pin on the IC should be connected to the 5V power plane through its own via. * Power MOSFET Gate Drive Trace. - The gate drive trace should be routed on one layer only. - The controller IC and the power FET should be oriented in such a way as to minimize the trace length of the gate drive trace (< 1 inch). - The gate drive trace routing should stay away from the quiet analog section of the RC50XX controller IC. (i.e. keep away from Vref, IFB, VFB, and CEXT.) * Bulk Capacitance. - The input bulk capacitance needs to be located less than 1" from the drain of the power MOSFET. We recommend the following guidelines for the amount of bulk input capacitance: * For an output load of <10A use 2 X 1500F caps. * For an output load of >10A use 3 X 1500F caps. - The output bulk capacitors should be located as close to the CPU socket as possible. We recommend the following guidelines for the amount of bulk output capacitance: * For Pentium Pro use 4 X 1500F. * For P55C MMX Pentium/ AMD K6 use 2X 1500F. * For Pentium II use 7 X 1500F.
3.
4.
5.
6.
16
PRODUCT SPECIFICATION
RC5050
* Inductor Location. The inductor should be located near to the Source of the Power MOSFET. The ideal condition would be to use an internal power plane to connect the Source of the power MOSFET, the inductor, and the flyback schottky diode together. * Sense Resistor. - The sense resistor should be located next to the inductor. - The two traces that run from the sense resistor to the RC50XX controller IC should be minimum width traces and be run parallel to each other. We recommend these sense resistor values: * For Pentium Pro use 0.006. * For P55C MMX Pentium/ AMD K6 use 0.007. * For Pentium II use 0.006. * Ground Plane. The RC50XX controller IC have a continuous ground plane running underneath the entire chip area. Each of the IC ground pins should have a separate via connection down into the ground plane. * Input Filter. In many high current DC-DC converter designs, it is advisable to add an input inductor in order to create an input filter. An inductor on the order of 1-3uH is usually all that is required to perform the filter. When this component is added to the circuit, it is important that the RC50XX controller IC receive its VCC power from the system side of the input inductor and not the "dirty" side of the inductor. (ie the side that is connected to the power MOSFET drains)
* To Minimize Electromagnetic Interference (EMI). - Avoid long ground connections. Connect directly to the ground plane. - Use a star ground, where all grounds are connected to one point. - Use good quality inductors such as torrids or pot cores. Avoid rod inductors. - Route the high current carrying traces as power planes where possible. - Keep sensitive low-level signals away from the active switching components. Try to route them using the ground plane as a shield.
Example of a PC Motherboard Layout and Gerber File
A reference design for motherboard implementation of the RC5050 along with the Layout Gerber File and Silk Screen are presented below. The actual PCAD Gerber File can be obtained from a Raytheon Electronics local Sales Office or from Marketing at 650-966-7734.
RC5050 Evaluation Board
Raytheon Electronics provides an evaluation board for the purpose of verifying the system level performance of the RC5050. The evaluation board serves as a guide as to what can be expected in performance with the supplied external components and PCB layout. Please call your local Sales Office or Raytheon Electronics Marketing department at 650-966-7734 for an evaluation board.
17
RC5050
PRODUCT SPECIFICATION
18
PRODUCT SPECIFICATION
RC5050
Mechanical Dimensions - 20 Lead SOIC
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
19

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